Writing to a memory cell or cells of static memories, such as static random access memories (SRAMs), multiple port memories, and First In First Out (FIFO) Memories, can sometimes affect adjacent memory cells on the same column that share a bitline. These memory cells should not be affected if their wordlines are off; however, leakage from a memory cell node to a bitline may be enough to overcome the pull-up resistance of the memory cell, causing the data of the memory cell to be corrupted. This problem is exacerbated by a long write cycle, because there is greater opportunity for such leakage to occur. Therefore, memory cell node to bitline leakage and subsequent corruption of memory cells is often a concern during long write cycle operation of a static memory.
The long write cycle problem occurs when writing to a selected memory cell in a column inadvertently affects the contents of non-selected memory cells in the same column, whose wordlines are off. If a memory cell has leakage from one of its storage nodes through the pass transistor to the bitline at a differential voltage from the storage node, an erroneous change of state can occur if the duration of the write cycle draws enough charge from the memory cell node to switch the cell state.
In order to screen memory devices that are sensitive to leakage during long write cycles, long write cycle testing is conducted in the manufacturing testing process by first writing a test data pattern to selected memory cells of a static memory. A long write cycle is then performed, typically on the order of microseconds, providing enough time for the leakage to cause a change of state in memory cells that have leaky pass transistors. This screening has been made more efficient by including special test modes in memory devices (in contrast to normal operating modes), in which the long write cycle is accomplished by turning off all wordlines of the memory, and pulling down either the true or complement bitline throughout the entire memory array, or a subset of the memory array, "disturbing" the memory cells. The memory cells are then read following the disturb condition to check for errors in the states of individual memory cells.
However, two issues must be considered before adopting such a special test mode in a memory design. First, the data states of both the memory cell under test and its adjacent memory cells, on all sides, can be critical in determining whether the memory cell has a propensity to be disturbed during long write testing. For instance, memory cells tend to fail on either the bitline true or the bitline complement side of the cell, because only one side of a memory cell usually leaks, in which case the likelihood of a memory cell to fail will depends upon the data state stored therein. Additionally, adjacent memory cells frequently share common connections to power supplies. Therefore, the stored data state of the memory cell under test, the stored data states of adjacent memory cells, and the shared common power supply connections of neighboring memory cells are all factors which can greatly affect the sensitivity of a memory cell to long write cycle disturbs.
Second, in order to pull down multiple bitlines of a memory cell, it is necessary to first turn off the bitlines in order to decrease power consumption. Incorporating the necessary bitline control to turn off appropriate bitline loads and pull bitlines to ground during the disturb for the various test data patterns to which a static memory is typically subjected necessarily introduces complicated circuitry to perform the requisite independent bitline load control function. Such complicated circuitry takes up valuable space within the static memory. A possible solution to these competing interests is to pull low the bitline true for all memory cells being tested while leaving the bitline complement high for all memory cells being tested, and vice versa for a second pass; alternatively, another simple pattern may be used. However, such schemes have limited practical use, because they do not address the great number of different test data patterns typically used to test static memories.
It is therefore an object of the present invention to provide a long write testing method which effectively and efficiently tests memory cells of a static memory for leakage problems using minimal control circuitry.
It is a further object of the present invention to provide a memory structure which provides for effective and efficient long write testing of static memory cells so that memory cells which have leakage problems may be identified using minimal control circuitry.
It is a further object of the present invention to provide a memory that can effect such long write testing by pulling both bitlines in a differential bitline architecture to a reference voltage.
It is a further object of the present invention to provide a method and circuit for controlling the pulling of bitlines to the reference voltage without requiring an additional external terminal.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.